Design verification has been the biggest challenge for any IC design company for decades now. EDA tools and verification methods have evolved a lot over the last two decades, but along with that, the ...

SAN FRANCISCO — Faraday Technology said Tuesday (Aug. 1) that its memory compilers are now integrated with Novas Software Inc.'s Verdi automated debug system, enabling joint customers to simulate and ...

Verification engineers tackling complex SoCs and FPGA designs can now simulate, debug, and optimize with greater speed and confidence, discover how its high-performance engines, broad language support ...

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by Cadence at the recent Design and Verification Conference (DVCon) in Santa Clara, CA ...

The VeriLogger Extreme compiled-code Verilog 2001 simulator promises to significantly reduce simulation debug time and offers fast simulation of both RTL and gate-level simulations with SDF timing ...

I hate race conditions. Developers of multithreaded applications who have bugs that are dependent upon the timing both within and between threads curse race conditions. They go against every instinct ...

HENDERSON, Nevada – November 17th, 2008 - Aldec, Inc., announced today Riviera-PRO 2008.10, a behavioral and structural HDL mixed-language simulator for multi-million gate ASIC and FPGA designs.

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, ...